1. Field of the Invention
The present invention relates to computer software for automatically generating an integrated circuit layout.
2. Description of Related Art
FIG. 1 illustrates a typical integrated circuit (IC) design process flow. An IC designer usually begins the IC design process by producing a register transfer language (RTL) xe2x80x9cnetlistxe2x80x9d 10 describing the IC circuit as a set of nets (signal paths) interconnecting terminals of circuit devices. In a high level RTL netlist circuit devices may be described in terms of the logic they carry out using Boolean expressions to define logical relationships between device input and output signals. After employing circuit simulation and verification tools 11 to check the logic of the IC described by RTL level netlist 10, the designer uses a syntheses tool 12 to convert RTL level netlist 10 into a xe2x80x9cgate levelxe2x80x9d netlist 14 describing the IC as a collection of cells having terminals interconnected through the nets. A xe2x80x9ccellxe2x80x9d is a circuit component described by a cell library 13 containing an entry for each cell that may be incorporated into an IC design. The library entry for each cell describes the cell""s layout. Cells may range from very small device such as individual transistors, to small components such as logic gate formed by several transistors, up to very large components such as computer processors and memories. Gate level netlist 14 incorporates each cell into the IC design by referring to an entry in cell library 13 describing the cell.
The entry for each cell in cell library 13 also provides a model of the time-dependent behavior of the cell that represent the cell when gate level netlist 14 is subjected to simulation and verification 11. A simulation based on gate level netlist 14 more accurately predicts the behavior of the IC than a simulation based on RTL level netlist 10. However since the gate level netlist 14 does not model the signal routing paths between the cells, the simulation and verification results at this stage of the design do not take into account signal path delays between the cells.
After verifying the behavior of the circuit described by gate level netlist 14, the circuit designer employs computer-aided placement and routing (PandR) tools 16 to convert gate level netlist 14 into an IC layout describing how each cell is to be formed and positioned within a semiconductor substrate and describing the signal routing paths within the IC that are to interconnect the cells. Cell library 13 tells PandR tools 16 how to lay out each cell, and the PandR tools determine where to place each cell in the substrate and how to route signal paths between them.
As PandR tools 16 create an IC layout, a xe2x80x9cnetlist updaterxe2x80x9d 20 updates the gate level netlist 14 to produce a xe2x80x9clayout levelxe2x80x9d netlist 22 modeling not only the cells forming the IC but also the routing structures that interconnect the cells. After PandR tools 16 have produced a layout 18, the designer may then again use simulation and verification tools 11 to verify the behavior of the circuit based on the more accurate layout level netlist 22 before sending the completed IC layout 18 to an IC manufacturer. Should layout 18 fails to satisfy all design constraints, the designer may try to resolve problems by using PandR tools 16 to alter layout 18. If that approach fails, the designer may try altering gate level netlist 14 and then repeating the placement and routing process.
Placement and Routing Tools
FIG. 2 illustrates a typical example of an iterative placement and routing process carried out at step 15 of FIG. 1. The designer may initially create a floor plan (step 24) for the layout when particular areas of the semiconductor substrate are to be reserved for particular cells. A PandR tool then develops a placement plan (step 26) indicating where each cell referenced by gate level netlist 14 is to be placed and how it is to be oriented within a semiconductor substrate in a manner consistent with the floor plan. Thereafter the PandR tool develops a routing plan (step 28) describing the routing structures that implement the nets interconnecting cell terminals. The placement and routing process (steps 26 and 28) is iterative in that when the PandR tool is unable to develop a routing plan a step 28 providing a suitable route for every net of the design, it alters the placement plan at (step 26) to reposition the cells, and then attempts to develop a suitable routing plan for the altered placement plan at step 28.
Within most digital ICs, signals pass between blocks of logic through clocked devices such as registers and flip-flops so that the clock signals clocking those devices can synchronize the timing with which the logic blocks pass signals to one another. The logic blocks are therefore subject to timing constraints in that they must be able to process their input signals to produce their output signals within the period between edges of the clock signal that clock their input and output signals. The time required for a logic block to process its input signals is a function of the processing speed of each cell within the logic block involved in the signal processing, and is also a function of the signal path delays through the various routing structures interconnecting those cells. Although the placement and routing tools may find space in the layout for all cells and for all of the routing structures interconnecting them at steps 26 and 28, the path delays through some of the logic blocks may fail to meet timing constraints.
Thus after the PandR tools have established placement and routing plans at steps 26 and 28, it is necessary to verify that all logic block meet their timing constraints. To do so, an RC extraction tool initially processes routing plan (step 30) to determine resistances and capacitances of the various sections of signal paths defined by the routing plan and passes that information to a timing analysis tool. Since the path delay though a conductor is a function of its resistance and capacitance (path inductance is usually neglected) the timing analysis tool (at step 32) is able to compute path delays through the various routing structures based on the resistance and capacitance information provided by the RC extraction tool. The timing analysis tool also consults the cell library to determine the path delay through each cell of interest. Based on the information provided by timing analysis tool, the placement and routing plans are subjected to an xe2x80x9cin place optimizationxe2x80x9d process (step 34) in which the path delays through the various logic blocks are analyzed to determine whether they meet their timing constraints. When a logic block fails to meet a timing constraint, the placement plan can be incrementally modified (step 35) by inserting buffers in signal paths to reduce path delays or by moving cells of the logic block closer together to reduce path delays between the cells. The routing plan is then altered (step 28) a necessary to accommodate the altered placement plan. The RC extraction (step 30) and timing analysis processes (step 32) are also repeated. The process iterates through steps 28, 30, 32, 34 and 35 until placement and routing plans satisfying all timing constraints are established.
The layout process may also include a step of checking the layout for various signal integrity problems (step 36) including, for example, static timing analysis and cross-talk analysis, and iteratively modifying the placement and routing plans (step 35) to resolve these problems.
When all signal integrity problems are resolved, a clock tree synthesis tool designs one or more clock trees (step 37) for the IC. A clock tree is a network of buffers for distributing a clock signal to the various registers, flip-flops and other clocked circuit devices. The clock tree design indicates an approximate position of each buffer forming the clock tree and routing paths interconnecting the buffers that will ensure that each clock signal edge arrives all clocked devices at substantially the same time. After the clock tree has been designed, the placement and routing plans are modified (steps 35 and 28) as necessary to fix the positions of the buffers forming the clock tree and the signal paths interconnecting them. The timing analysis and in-place optimization steps 32 and 34 may then be repeated to verify that the change in placement and routing needed to accommodate the clock tree has not adversely affected the ability of the IC layout to meet all timing constraints. If, so steps 35, 28, 30, and 34 are repeated as necessary to adjust the layout to meet its timing constraints. A power analysis step 39 is also be carried out in which the layout is analyzed to determine whether the power loads are adequately distributed throughout the power distribution network that delivers power to all cells. When the layout process is unable to produce a layout based on gate level netlist 14 that satisfies all constraints, it may be necessary at step 40 to restructure the logic of the IC design (i.e. to modify gate level netlist 14) and then repeat the entire placement and routing process.
The IC layout process illustrated in FIG. 2 can be very time-consuming, particularly for large, tightly constrained IC designs. Routing step 28 consumes much of the processing time because developing and modifying a routing plan is computationally expensive and because routing step 28 must be revisited many times during the iterative layout process following iterative modifications to the placement plan as a result of steps 34, 36, 37, 39 and 40.
What is needed is an improved layout process flow that reduces the amount of time spent on developing and modifying the routing plan.
In accordance with the invention an integrated circuit (IC) layout process is organized into two phases. During the Phase 1 of the process, a preliminary placement plan is developed fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is then developed establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets all defined signal path timing, signal integrity, and power distribution and other constraints.
Thereafter, at the start of Phase 2 of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the routes followed all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.
The invention speeds up the layout process by delaying the need to create and update a detailed routing plan until Phase 2 of the process. During Phase 1 of the process, a routing tool can create and iterative modify the trial layout very quickly because it is necessary for the routing tool to terminate the nets in the vicinity of the cell terminals to which they are to be connected and not exactly on them, and it is not necessary for the routing tool to spend time looking for and correcting routing conflicts. However, although the trial routing plan only approximates net routes, it nonetheless provides a basis for estimating signal path delays with sufficient accuracy to permit the various constraint checking tools to determine whether the layout is likely to meet all timing constraints when the trial routing plan is converted to a detailed routing plan at the start of Phase 2 of the process. Thus when the layout process enters Phase 2 and converts the trial routing plan to a detailed routing plan, it normally requires only a relatively few iterative modifications to the placement plan and the detailed routing plans to produce a layout meeting all constraints. The total time required to carry out both Phase 1 and Phase 2 of the placement and routing process will typically be substantially less then the time need to carry out a prior art process which initially creates and iteratively updates a detailed routing plan. The two-phase process flow in accordance with the invention provides a particularly large speed advantage over the conventional approach when used to lay out a large, tightly constrained IC requiring many iterative placement and routing plan modifications to satisfy all design constraints.
The claims appended to this specification particularly point out and distinctly claim the subject matter of the invention. However those skilled in the art will best understand both the organization and method of operation of what the applicant(s) consider to be the best mode(s) of practicing the invention, together with further advantages and objects of the invention, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.